Industrial partner TERMA is producing radar sensors mainly used for traffic control in ports and airports and for coastal surveillance. The real-time processing of radar signals includes integration of several received signals, requiring the signals to be stored temporarily in memory. The interface between the signal processing hardware and the memory consists of an arbiter and a collection of 9 FIFO buffers. During processing the buffers are not allowed to become empty or overflow. The arbiter includes a scheduling algorithm deciding when to access the buffers. The aim of the case study is to verify that the behaviour of the scheduling algorithm is correct. A second step will be to synthesise a scheduler for a set of integrators and buffers. This is particular interesting for TERMA as the next generation of radar sensors will include similar memory interfaces, though with increased demands on access to the memory.